feat(core/asm): add instruction encoder
This commit is contained in:
dualfroz committed
1 parent
2004647201
commit
416348a9aa
1 file changed
+362
@@ -0,0 +1,362 @@
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using System;
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using System.Collections.Generic;
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namespace Chip8.Core.Assembly;
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public static class InstructionEncoder
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{
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public static int measure(InstructionStatement instruction, Func<Token, int> resolver)
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{
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if (isLongLoad(instruction, resolver))
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{
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return 4;
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}
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return 2;
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}
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public static void emit(InstructionStatement instruction, Func<Token, int> resolver, List<byte> output)
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{
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string mnemonic = instruction.mnemonic.ToUpperInvariant();
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IReadOnlyList<Operand> operands = instruction.operands;
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switch (mnemonic)
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{
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case "CLS": zeroOperands(instruction); writeWord(output, 0x00E0); return;
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case "RET": zeroOperands(instruction); writeWord(output, 0x00EE); return;
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case "SCR": zeroOperands(instruction); writeWord(output, 0x00FB); return;
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case "SCL": zeroOperands(instruction); writeWord(output, 0x00FC); return;
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case "EXIT": zeroOperands(instruction); writeWord(output, 0x00FD); return;
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case "LORES":
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case "LOW": zeroOperands(instruction); writeWord(output, 0x00FE); return;
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case "HIRES":
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case "HIGH": zeroOperands(instruction); writeWord(output, 0x00FF); return;
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case "AUDIO": zeroOperands(instruction); writeWord(output, 0xF002); return;
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case "SCD": writeWord(output, (ushort)(0x00C0 | nibble(singleImmediate(instruction, resolver), instruction, "SCD"))); return;
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case "SCU": writeWord(output, (ushort)(0x00D0 | nibble(singleImmediate(instruction, resolver), instruction, "SCU"))); return;
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case "PLANE": writeWord(output, (ushort)(0xF001 | (nibble(singleImmediate(instruction, resolver), instruction, "PLANE") << 8))); return;
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case "JP": encodeJump(instruction, resolver, output); return;
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case "CALL": writeWord(output, (ushort)(0x2000 | address(singleImmediate(instruction, resolver), instruction, "CALL"))); return;
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case "SE": encodeSkip(instruction, resolver, output, 0x3000, 0x5000); return;
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case "SNE": encodeSkip(instruction, resolver, output, 0x4000, 0x9000); return;
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case "OR": encodeArithmetic(instruction, output, 0x1); return;
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case "AND": encodeArithmetic(instruction, output, 0x2); return;
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case "XOR": encodeArithmetic(instruction, output, 0x3); return;
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case "SUB": encodeArithmetic(instruction, output, 0x5); return;
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case "SUBN": encodeArithmetic(instruction, output, 0x7); return;
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case "SHR": encodeShift(instruction, output, 0x6); return;
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case "SHL": encodeShift(instruction, output, 0xE); return;
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case "ADD": encodeAdd(instruction, resolver, output); return;
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case "LD": encodeLoad(instruction, resolver, output); return;
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case "RND":
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requireOperands(instruction, 2);
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writeWord(output, (ushort)(0xC000 | (register(operands[0], "RND") << 8) | byte8(immediate(operands[1], resolver), instruction, "RND")));
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return;
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case "DRW":
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requireOperands(instruction, 3);
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writeWord(output, (ushort)(0xD000 | (register(operands[0], "DRW") << 8) | (register(operands[1], "DRW") << 4) | nibble(immediate(operands[2], resolver), instruction, "DRW")));
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return;
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case "SKP":
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requireOperands(instruction, 1);
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writeWord(output, (ushort)(0xE09E | (register(operands[0], "SKP") << 8)));
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return;
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case "SKNP":
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requireOperands(instruction, 1);
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writeWord(output, (ushort)(0xE0A1 | (register(operands[0], "SKNP") << 8)));
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return;
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case "PITCH":
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requireOperands(instruction, 1);
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writeWord(output, (ushort)(0xF03A | (register(operands[0], "PITCH") << 8)));
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return;
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case "SAVE": encodeRange(instruction, output, 0x2); return;
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case "LOAD": encodeRange(instruction, output, 0x3); return;
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default:
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throw new AsmException("unknown mnemonic '" + instruction.mnemonic + "'", instruction.position);
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}
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}
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static void encodeJump(InstructionStatement instruction, Func<Token, int> resolver, List<byte> output)
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{
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IReadOnlyList<Operand> operands = instruction.operands;
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if (operands.Count == 1)
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{
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writeWord(output, (ushort)(0x1000 | address(immediate(operands[0], resolver), instruction, "JP")));
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return;
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}
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if (operands.Count == 2 && operands[0].isRegister(0))
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{
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writeWord(output, (ushort)(0xB000 | address(immediate(operands[1], resolver), instruction, "JP")));
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return;
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}
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throw new AsmException("JP expects an address or 'V0, address'", instruction.position);
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}
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static void encodeSkip(InstructionStatement instruction, Func<Token, int> resolver, List<byte> output, int immediateBase, int registerBase)
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{
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requireOperands(instruction, 2);
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IReadOnlyList<Operand> operands = instruction.operands;
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int x = register(operands[0], instruction.mnemonic);
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if (operands[1].kind == OperandKind.Register)
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{
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writeWord(output, (ushort)(registerBase | (x << 8) | (operands[1].registerIndex << 4)));
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return;
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}
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writeWord(output, (ushort)(immediateBase | (x << 8) | byte8(immediate(operands[1], resolver), instruction, instruction.mnemonic)));
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}
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static void encodeArithmetic(InstructionStatement instruction, List<byte> output, int op)
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{
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requireOperands(instruction, 2);
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IReadOnlyList<Operand> operands = instruction.operands;
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int x = register(operands[0], instruction.mnemonic);
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int y = register(operands[1], instruction.mnemonic);
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writeWord(output, (ushort)(0x8000 | (x << 8) | (y << 4) | op));
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}
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static void encodeShift(InstructionStatement instruction, List<byte> output, int op)
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{
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IReadOnlyList<Operand> operands = instruction.operands;
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if (operands.Count is < 1 or > 2)
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{
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throw new AsmException(instruction.mnemonic + " expects 'Vx' or 'Vx, Vy'", instruction.position);
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}
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int x = register(operands[0], instruction.mnemonic);
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int y = operands.Count == 2 ? register(operands[1], instruction.mnemonic) : 0;
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writeWord(output, (ushort)(0x8000 | (x << 8) | (y << 4) | op));
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}
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static void encodeAdd(InstructionStatement instruction, Func<Token, int> resolver, List<byte> output)
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{
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requireOperands(instruction, 2);
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IReadOnlyList<Operand> operands = instruction.operands;
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if (operands[0].kind == OperandKind.IndexRegister)
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{
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writeWord(output, (ushort)(0xF01E | (register(operands[1], "ADD") << 8)));
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return;
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}
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int x = register(operands[0], "ADD");
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if (operands[1].kind == OperandKind.Register)
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{
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writeWord(output, (ushort)(0x8004 | (x << 8) | (operands[1].registerIndex << 4)));
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return;
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}
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writeWord(output, (ushort)(0x7000 | (x << 8) | byte8(immediate(operands[1], resolver), instruction, "ADD")));
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}
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static void encodeLoad(InstructionStatement instruction, Func<Token, int> resolver, List<byte> output)
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{
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requireOperands(instruction, 2);
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Operand destination = instruction.operands[0];
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Operand source = instruction.operands[1];
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switch (destination.kind)
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{
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case OperandKind.Register:
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encodeLoadIntoRegister(instruction, destination.registerIndex, source, resolver, output);
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return;
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case OperandKind.IndexRegister:
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encodeLoadIndex(instruction, source, resolver, output);
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return;
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case OperandKind.DelayTimer:
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writeWord(output, (ushort)(0xF015 | (register(source, "LD DT") << 8)));
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return;
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case OperandKind.SoundTimer:
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writeWord(output, (ushort)(0xF018 | (register(source, "LD ST") << 8)));
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return;
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case OperandKind.FontReg:
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writeWord(output, (ushort)(0xF029 | (register(source, "LD F") << 8)));
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return;
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case OperandKind.BigFontReg:
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writeWord(output, (ushort)(0xF030 | (register(source, "LD HF") << 8)));
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return;
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case OperandKind.BcdReg:
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writeWord(output, (ushort)(0xF033 | (register(source, "LD B") << 8)));
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return;
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case OperandKind.IndexIndirect:
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writeWord(output, (ushort)(0xF055 | (register(source, "LD [I]") << 8)));
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return;
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case OperandKind.RplReg:
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writeWord(output, (ushort)(0xF075 | (register(source, "LD R") << 8)));
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return;
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default:
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throw new AsmException("unsupported LD destination", instruction.position);
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}
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}
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static void encodeLoadIntoRegister(InstructionStatement instruction, int x, Operand source, Func<Token, int> resolver, List<byte> output)
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{
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switch (source.kind)
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{
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case OperandKind.Register:
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writeWord(output, (ushort)(0x8000 | (x << 8) | (source.registerIndex << 4)));
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return;
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case OperandKind.DelayTimer:
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writeWord(output, (ushort)(0xF007 | (x << 8)));
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return;
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case OperandKind.KeyReg:
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writeWord(output, (ushort)(0xF00A | (x << 8)));
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return;
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case OperandKind.IndexIndirect:
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writeWord(output, (ushort)(0xF065 | (x << 8)));
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return;
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case OperandKind.RplReg:
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writeWord(output, (ushort)(0xF085 | (x << 8)));
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return;
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case OperandKind.Immediate:
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writeWord(output, (ushort)(0x6000 | (x << 8) | byte8(immediate(source, resolver), instruction, "LD")));
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return;
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default:
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throw new AsmException("unsupported LD source", instruction.position);
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}
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}
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static void encodeLoadIndex(InstructionStatement instruction, Operand source, Func<Token, int> resolver, List<byte> output)
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{
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if (source.kind != OperandKind.Immediate)
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{
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throw new AsmException("LD I expects an address", instruction.position);
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}
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int value = immediate(source, resolver);
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if (value is < 0 or > 0xFFFF)
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{
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throw new AsmException("index value 0x" + value.ToString("X") + " out of 16-bit range", instruction.position);
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}
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if (value > 0xFFF)
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{
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writeWord(output, 0xF000);
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writeWord(output, (ushort)value);
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return;
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}
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writeWord(output, (ushort)(0xA000 | value));
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}
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static void encodeRange(InstructionStatement instruction, List<byte> output, int op)
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{
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requireOperands(instruction, 1);
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Operand operand = instruction.operands[0];
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if (operand.kind != OperandKind.RegisterRange)
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{
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throw new AsmException(instruction.mnemonic + " expects a 'Vx-Vy' register range", instruction.position);
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}
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writeWord(output, (ushort)(0x5000 | (operand.registerIndex << 8) | (operand.rangeEnd << 4) | op));
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}
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static bool isLongLoad(InstructionStatement instruction, Func<Token, int> resolver)
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{
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if (!string.Equals(instruction.mnemonic, "LD", StringComparison.OrdinalIgnoreCase))
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{
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return false;
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}
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IReadOnlyList<Operand> operands = instruction.operands;
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if (operands.Count != 2 || operands[0].kind != OperandKind.IndexRegister || operands[1].kind != OperandKind.Immediate)
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{
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return false;
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}
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return immediate(operands[1], resolver) > 0xFFF;
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}
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static int singleImmediate(InstructionStatement instruction, Func<Token, int> resolver)
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{
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requireOperands(instruction, 1);
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return immediate(instruction.operands[0], resolver);
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}
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static int immediate(Operand operand, Func<Token, int> resolver)
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{
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if (operand.kind != OperandKind.Immediate)
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{
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throw new AsmException("expected a numeric operand but found " + operand, operand.position);
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}
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return Expression.evaluate(operand.expressionTokens, resolver, operand.position);
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}
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static int register(Operand operand, string mnemonic)
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{
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if (operand.kind != OperandKind.Register)
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{
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throw new AsmException(mnemonic + " expects a V register but found " + operand, operand.position);
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}
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return operand.registerIndex;
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}
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static int nibble(int value, InstructionStatement instruction, string mnemonic)
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{
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if (value is < 0 or > 0xF)
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{
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throw new AsmException(mnemonic + " nibble 0x" + value.ToString("X") + " out of range (0-15)", instruction.position);
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}
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return value;
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}
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static int byte8(int value, InstructionStatement instruction, string mnemonic)
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{
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if (value is < 0 or > 0xFF)
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{
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throw new AsmException(mnemonic + " byte 0x" + value.ToString("X") + " out of range (0-255)", instruction.position);
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}
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return value;
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}
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static int address(int value, InstructionStatement instruction, string mnemonic)
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{
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if (value is < 0 or > 0xFFF)
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{
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throw new AsmException(mnemonic + " address 0x" + value.ToString("X") + " out of range (0-0xFFF)", instruction.position);
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}
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return value;
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}
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static void requireOperands(InstructionStatement instruction, int count)
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{
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if (instruction.operands.Count != count)
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{
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throw new AsmException(
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instruction.mnemonic + " expects " + count + " operand(s), got " + instruction.operands.Count,
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instruction.position);
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}
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}
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static void zeroOperands(InstructionStatement instruction)
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{
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if (instruction.operands.Count != 0)
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{
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throw new AsmException(instruction.mnemonic + " takes no operands", instruction.position);
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}
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}
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static void writeWord(List<byte> output, ushort value)
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{
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output.Add((byte)(value >> 8));
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output.Add((byte)(value & 0xFF));
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}
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}
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